A flash EEPROM (electrically erasable and programmable ROM) cell is formed with including a floating gate and a control gate. Such a flash memory cell is erased by discharging electrons of the floating gate to its substrate through an F-N tunneling effect when a high negative voltage is applied to a control gate of the memory cell. A flash memory cell array is normally divided in a plurality of sectors (or blocks) by the unit of bulks. Thus, memory cells includes in a sector, sharing one bulk, are contemporaneously erased in a time, which is called “sector erase” in general.
Receiving commands and sector addresses for sectors to be erased, an internal address counter increments an address value in sequence to designate the erasable sectors. Such a function to contemporaneously erase a multiplicity of sectors is called as a multi-sector erase operation.
The multi-sector erase operation, basically, needs registers with the same number of the sectors to be erased, and means to erase the sectors in response to the determination a current sector is an erasable sector in correspondence with the incrementing address.
A typical feature of the multi-sector erase scheme is illustrated in FIG. 1, for 128 sectors as an example in a single chip. The 128 sectors are assigned to sector addresses SA0˜SA127. In this embodiment, it is assumed to designate the sector assigned to the address SA3.
An erase command and an address for a sector to be erased are supplied from an external controller. The external controller may supply a single address to erase a single sector or a plurality of addresses to erase a plurality of sectors in a time, which is referred to as “multi-sector erase” in a single chip. Such an address supply for the erase operation is called as “sector loading”.
FIG. 2 shows a functional construction for a single multi-sector erase operation in a single chip. A memory cell array 60 is also composed of a plurality of sectors. A register 10 stores addresses of sectors to be erased. A counter 30 generates sequential addresses in response to an address count-up signal ACNT. A control circuit 40 generates an erase enable signal EE when the sector address held in the register 10 is identified to a sector address provided from the counter 30, while generating the address count-up signal ACNT when the two addresses do not accord with each other. A core driver 50 carries out an erase operation for a sector designated therein in response to the erase enable signal EE.
FIGS. 3 and 4 illustrate a procedure of the multi-sector erase operation in a single chip shown in FIG. 2.
Referring to FIGS. 3 and 4, first, an erase command and a sector address (e.g. SA3) are introduced by way of an external controller. With the input of the erase command, the sector address SA3 to be erased is stored in the register 10. The register 10 is assigned to the sector each by each. The register 10 corresponding to the sector to be erased is set to “1” (binary digit), which informs the predetermination for erasing.
The multi-sector erase operation begins with an activation of an erase busy signal EB, together with the input of the erase command and sector address. At the beginning of the erase operation, the control circuit 40 initiates the address counter 30 on “0”, which means all address values of the counter 30 are set to “0” (step S11). For instance, assuming that the memory cell array 60 is composed of 128 (27) sectors, all bits of the sector address SA[6:0] are set to “0”. Next, the control circuit 40 generates a sector checking signal SC to determine an advance for a sector whose address is compared to the sector address (e.g., SA3) stored in the register 10 (step S12).
From the first sector address SA0, as the first sector address SA0 is not identical to the assigned sector address SA3, the control circuit 40 generates the address count-up signal ACNT to increment the sector address by the counter 30 (S15). Along the increment of the sector address, the control circuit 40 keeps checking out the sector address next to next. If a sector address supplied from the counter 30 is identical to the sector address SA3 held in the register 10, a sector loading signal LS is transferred to the control circuit 40 from the register 10. The sector loading signal LS makes an erase enable signal EE generated from the control circuit 40. The erase enable signal EE enables the core driver 50 to carry out an erase operation for the sector SA3 (step S13). In step S14, if a current sector address from the counter 30 is not the last one, it goes to the step S15 to increment the address value. The current sector address form the counter 30 reaches to the last one (e.g., SA127), the counter 30 generates a sector address finalizing signal FSA to be transferred to the control circuit 40. Then, the control circuit 40 generates an erase finish signal EF to terminate the erase operation for the assigned sector SA3.
Meanwhile, multi-chip packages are becoming standard in the IC industry because of increased device packing density, in which a plurality of semiconductor IC chips are fabricated with interconnections. A multi-chip memory package embedding a plurality of semiconductor memory chips acts as a single memory system having a large storage capacity of twice or more, which is advantageous to reducing manufacturing costs as well as to adapting for larger storage applications with smaller device volumes.
When the flash memories composed of a multiplicity of sectors and operable in the multi-sector erase modes are fabricated in such multi-chip packages, it needs to implement the multi-sector erase operations for the sectors of the flash memory chips contained in such a multi-chip memory package.